Resilient Orbital Computing

We propose developing a comprehensive framework enabling Circuit-Error-
Detection Code (EDC) co-design for reliable scientific computing. Our approach uniquely combines
formal verification using Satisfiability Modulo Theories (SMT) with statistical Monte Carlo fault
injection to evaluate how Arithmetic Error Detection Codes (AEDCs) protect real gate-level circuits.
Unlike traditional approaches treating codes and hardware separately, our framework reveals how
circuit topology and code selection interact, providing protection exceeding theoretical predictions.