qTEC

Overview

**One-line description.** Theory-driven architecture of fault-tolerant
low-precision compute for neural-network inference.

**Key claim.** Algorithm-Based Fault Tolerance (ABFT) over the chain ring
$\mathbb{Z}/2^n$ can supply reliability guarantees at lower silicon overhead
than per-bit ECC, *provided* the generator, redundancy level, and accumulator
width are chosen by theory rather than tuned empirically.

**Methodology.** Theoretical track: develop coding theory over chain rings,
prove miscorrection bounds via 2-adic valuation accounting and the
lifting-the-exponent lemma. Architectural track: synthesize a reference RTL
MAC array in commercial PDK + FPGA prototype, with parameters derived from the
theory. Validate by cross-checking theoretical bounds against fault-injection
measurements at iso-SDC budget.

**Output target.** MS thesis + one venue paper. Subsidiary deliverables:
synthesizable RTL of a fault-tolerant integer MAC array, an exhaustive-enumeration
miscorrection verifier, and an iso-SDC comparison against per-bit ECC and TMR
across at least three orders of magnitude in target SDC.

**Primary references on this site.**

- qTEC Algebraic Theory —
theorem statements, proof sketches, fault classes, open problems.

**Out of scope** (intentionally narrow for a one-year MS thesis): end-to-end
LLM accuracy studies, floating-point kernels (FP4/FP8), beam-test fault data,
PyTorch/TVM compiler integration, multi-chip fault tolerance, reliability-aware
quantization (workload co-design).