Fault-Tolerant Arithmetic for Space Computing

As the area of arithmetic datapaths grows in modern hardware, driven by wide SIMD/vector units and systolic arrays, these circuits become a larger and more vulnerable target for radiation-induced faults and circuit aging. Yet, while memory is routinely protected with Error-Correcting Codes (ECCs), the ALU-heavy compute logic in CPUs and accelerators often lacks comparable protection.

This project introduces a hybrid formal and statistical framework designed to rigorously evaluate the reliability of arithmetic datapaths. By combining Satisfiability Modulo Theories (SMT) with Monte Carlo fault injection at the gate level, we analyze how Arithmetic Codes (such as AN and RRNS) inherently compatible with arithmetic operations interact with specific circuit topologies. Our framework proves that inherent logic masking in hardware significantly improves error detection capabilities beyond theoretical codebook predictions, enabling designers to tailor resilience for safety-critical deployments ranging from autonomous vehicles to particle accelerators.