Circuit-Aware Analysis of Arithmetic Error Detection Codes

In modern CMOS VLSI circuits, arithmetic datapaths are increasingly vulnerable to radiation-induced soft errors and circuit-aging, leading to application crashes or silent data corruption. However, existing studies lack a gate-level framework for evaluating the efficacy of arithmetic error-detection codes in the presence of logic and timing masking. We focus on arithmetic codes—such as AN codes and Redundant Residue Number System codes—that natively support arithmetic operations, unlike conventional linear block codes. We prioritize detection over correction given the low cost of re-execution and the rarity of radiation strikes relative to compute throughput. Because 48-bit values and pointers typically suffice in contemporary systems, we adopt a 48+16-bit (data+redundancy) organization. We introduce a statistical framework that models radiation strikes by injecting LET-based pulse-widths into netlists and emulates circuit-aging through delay scaling. The toolchain enables designers to screen arithmetic code schemes before tape-out and tailor resilience for deployments ranging from sea-level cosmic-ray exposure to the high-radiation conditions such as particle accelerators, spacecraft, and defense electronics. By exposing how code parameters and circuit topology interact at the gate level, the framework fosters tightly coupled code-hardware co-design.